LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 279
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
9.23.2 Types of CPU access
9.23.3 Overall bandwidth
9.24 CRC calculation
This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.
This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.
Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which
comes to approximately 66.5 MB/s.
The peak bandwidth requirement can be somewhat higher due to the use of small
memory buffers, in order to hold often used addresses (e.g. the station address) for
example. Driver software can determine how to build frames in an efficient manner that
does not overutilize the AHB.
The bandwidth available on the AHB bus depends on the system clock frequency. As an
example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses
related to the Ethernet will be word transfers. The raw AHB bandwidth can be
approximated as 4 bytes per two system clocks, which equals 2 times the system clock
rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization
for Ethernet traffic during simultaneous transmit and receive operations.
The calculation is used for several purposes:
The C pseudocode function below calculates the CRC on a frame taking the frame
(without FCS) and the number of bytes in the frame as arguments. The function returns
the CRC as a 32 bit integer.
•
•
•
•
•
– Data to be received in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
Accesses that mirror each of the DMA access types:
– All or part of status values must be read, and all or part of descriptors need to be
– This gives roughly the same or slightly lower rate as the combined DMA functions,
Access to registers in the Ethernet block:
– The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus
– 7 word read/writes once every 64 bytes (16 words) of transmitted and received
– This gives 7/16 of the data rate, which = 5.4688 Mbps.
Generation the FCS at the end of the Ethernet frame.
Generation of the hash table index for the hash table filtering.
Generation of the destination and source address hash CRCs.
written after each use, transmitted data must be stored in the memory by the CPU,
and eventually received data must be retrieved from the memory by the CPU.
which = 30.5 Mbps.
registers, and both read and write the RxConsumeIndex and TxProduceIndex
registers.
data.
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
279 of 792
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