LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 651
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004)
6.2.3 Clock Control Register (CCR - 0xE002 4008)
6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control
Register (CCR). The CTC consists of the bits of the clock divider counter.
Table 568. Clock Tick Counter Register (CTCR - address 0xE002 4004) bit description
If the RTC is driven by the external 32.786 kHz oscillator, subsequent read operations of
the CTCR may yield an incorrect result. The CTCR is implemented as a 15-bit ripple
counter so that not all 15 bits change simultaneously. The LSB changes first, then the
next, and so forth. Since the 32.786 kHz oscillator is asynchronous to the CPU clock, it is
possible for a CTC read to occur during the time when the CTCR bits are changing
resulting in an incorrect large difference between back-to-back reads.
If the RTC is driven by the PCLK, the CPU and the RTC are synchronous because both of
their clocks are driven from the PLL output. Therefore, incorrect consecutive reads can
not occur.
The clock register controls the operation of the clock divide circuit. Each bit of the clock
register is described in
Table 569. Clock Control Register (CCR - address 0xE002 4008) bit description
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
Bit
0
15:1
Bit
0
1
3:2
4
7:5
Symbol
-
Clock Tick
Counter
Symbol
CLKEN
CTCRST
-
CLKSRC
-
Description
Clock Enable. When this bit is a one the time counters are enabled.
When it is a zero, they are disabled so that they may be initialized.
CTC Reset. When one, the elements in the Clock Tick Counter are
reset. The elements remain reset until CCR[1] is changed to zero.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler,
as on earlier devices in the NXP Embedded ARM family. If this bit is 1,
the CTC takes its clock from the 32 kHz oscillator that’s connected to
the RTCX1 and RTCX2 pins (see
oscillator component selection”
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Prior to the Seconds counter, the CTC counts 32,768 clocks per
second. Due to the RTC Prescaler, these 32,768 time increments may
not all be of the same duration. Refer to the
“Reference Clock Divider (Prescaler)” on page 656
Rev. 04 — 26 August 2009
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
Table
26–569.
for hardware details).
Section 26–9 “RTC external 32 kHz
Section 26–6.7.1
for details.
UM10237
© NXP B.V. 2009. All rights reserved.
651 of 792
Reset
value
NA
NA
Reset
value
NA
NA
NA
NA
NA
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