LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 421
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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10. USB OTG controller initialization
UM10237_4
User manual
9.1.1 Host clock request signals
9.2 Power-down mode support
The dev_dma_need_clk signal is asserted on any Device controller DMA access to
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA
throughput is not affected by any latency associated with re-enabling ahb_master_clk.
2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve
power. This signal allows AHB_CLK_EN to be cleared during normal operation.
The Host controller has two clock request signals, host_need_clk and
host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and
ahb_master_clk respectively.
The host_need_clk signal is asserted while the Host controller functional state is not
UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a
disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared
during normal operation when software does not need to access the Host controller
registers – the Host will continue to function normally and automatically shut off its clock
when it goes into the UsbSuspend state.
The host_dma_need_clk signal is asserted on any Host controller DMA access to
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA
throughput is not affected by any latency associated with re-enabling ahb_master_clk.
2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve
power. This signal allows AHB_CLK_EN to be cleared during normal operation.
The LPC2400 can be configured to wake up from Power-down mode on any USB bus
activity. When the USBWAKE bit is set in the INTWAKE register, the assertion of the
USB_NEED_CLK signal causes the chip to wake up from Power-down.
Before Power-down mode can be entered when USBWAKE is set, USB_NEED_CLK
must be de-asserted. This is accomplished by clearing all of the CLK_EN bits in
OTGClkCtrl and putting the Host controller into the UsbSuspend functional state. If it is
necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be
de-asserted, the status of USB_NEED_CLK can be polled in the USBIntSt register to
determine when they have all been de-asserted.
The LPC2400 OTG device controller initialization includes the following steps:
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk, and
3. Enable the desired controller clocks by setting their respective CLK_EN bits in the
the desired frequency for cclk. For correct operation of synchronization logic in the
device controller, the minimum cclk frequency is 18 MHz. For the procedure for
determining the PLL setting and configuration, see
determining PLL
USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register
until they are set.
settings”.
Rev. 04 — 26 August 2009
Chapter 15: LPC24XX USB OTG controller
Section 4–3.2.12 “Procedure for
UM10237
© NXP B.V. 2009. All rights reserved.
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