LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 531
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
7. Register description
UM10237_4
User manual
7.1 SPI Control Register (S0SPCR - 0xE002 0000)
The SPI contains 5 registers as shown in
and word accessible.
Table 461. SPI register map
[1]
The S0SPCR register controls the operation of the SPI0 as per the configuration bits
setting.
Table 462: SPI Control Register (S0SPCR - address 0xE002 0000) bit description
Name
S0SPCR
S0SPSR
S0SPDR
S0SPCCR SPI Clock Counter Register. This register
S0SPINT
Bit
1:0
2
3
4
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
-
BitEnable
CPHA
CPOL
Description
SPI Control Register. This register controls the
operation of the SPI.
SPI Status Register. This register shows the
status of the SPI.
SPI Data Register. This bi-directional register
provides the transmit and receive data for the
SPI. Transmit data is provided to the SPI0 by
writing to this register. Data received by the SPI0
can be read from this register.
controls the frequency of a master’s SCK0.
SPI Interrupt Flag. This register contains the
interrupt flag for the SPI interface.
Value Description
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
The SPI controller sends and receives 8 bits of data per
transfer.
The SPI controller sends and receives the number of bits
selected by bits 11:8.
Clock phase control determines the relationship between
the data and the clock on SPI transfers, and controls
when a slave transfer is defined as starting and ending.
Data is sampled on the first clock edge of SCK. A transfer
starts and ends with activation and deactivation of the
SSEL signal.
Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with the
last sampling edge when the SSEL signal is active.
Clock polarity control.
SCK is active high.
SCK is active low.
Table
19–461. All registers are byte, half word
Access
R/W
RO
R/W
R/W
R/W
Chapter 19: LPC24XX SPI
Reset
Value
0x00
0x00
0x00
0x00
0x00
UM10237
© NXP B.V. 2009. All rights reserved.
[1]
Address
0xE002 0000
0xE002 0004
0xE002 0008
0xE002 000C
0xE002 001C
Reset
Value
NA
0
0
0
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