LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 639
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 557. PWM0 and PWM1 register map
[1]
UM10237_4
User manual
Generic
Name
MR4
MR5
MR6
PCR
LER
CTCR
Reset Value relects the data stored in used bits only. It does not include reserved bits content.
Description
Match Register 4. MR4 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM4 in either
edge mode, and sets PWM5 if it’s in double-edge mode.
Match Register 5. MR5 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM5 in either
edge mode, and sets PWM6 if it’s in double-edge mode.
Match Register 6. MR6 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM6 in either
edge mode.
PWM Control Register. Enables PWM outputs and
selects PWM channel types as either single edge or
double edge controlled.
Load Enable Register. Enables use of new PWM match
values.
Count Control Register. The CTCR selects between
Timer and Counter mode, and in Counter mode selects
the signal and edge(s) for counting.
6.1 PWM Interrupt Register (PWM0IR - 0xE001 4000 and PWM1IR
0xE001 8000)
The PWM Interrupt register consists of eleven bits
interrupts and four reserved. If an interrupt is generated then the corresponding bit in the
PWMIR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding
IR bit will reset the interrupt. Writing a zero has no effect.
Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address
Bit
0
1
2
3
4
5
7:6
8
Symbol
PWMMR0 Interrupt Interrupt flag for PWM match channel 0.
PWMMR1 Interrupt Interrupt flag for PWM match channel 1.
PWMMR2 Interrupt Interrupt flag for PWM match channel 2.
PWMMR3 Interrupt Interrupt flag for PWM match channel 3.
PWMCAP0
Interrupt
PWMCAP1
Interrupt
-
PWMMR4 Interrupt Interrupt flag for PWM match channel 4.
0xE001 8000) bit description
Rev. 04 — 26 August 2009
Description
Interrupt flag for capture input 0
Interrupt flag for capture input 1 (available in PWM1IR only;
this bit is reserved in PWM0IR).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
(Table
[1]
PWM0 Address
& Name
0xE001 4040
PWM0MR
0xE001 4044
PWM0MR
0xE001 4048
PWM0MR
0xE001 404C
PWM0PCR
0xE001 4050
PWM0LER
0xE001 4070
PWM0CTCR
25–558), seven for the match
UM10237
© NXP B.V. 2009. All rights reserved.
PWM1 Address
& Name
0xE001 8040
PWM1MR
0xE001 8044
PWM1MR
0xE001 8048
PWM1MR
0xE001 804C
PWM1PCR
0xE001 8050
PWM1LER
0xE001 8070
PWM1CTCR
639 of 792
Reset
Value
0
0
0
0
0
0
-
0
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