LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 92
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
10.21 Static Memory Configuration registers (EMCStaticConfig0-3 -
Table 88.
0xFFE0 8200, 220, 240, 260)
The EMCStaticConfig0-3 registers configure the static memory configuration. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
Table 5–89
synchronous burst mode memory devices are not supported.
Table 89.
Bit
9:8
31:10 -
Bit
1:0
2
3
5:4
6
Symbol
Memory width
(MW)
-
Page mode
(PM)
-
Chip select
polarity (PC)
Symbol
CAS latency
(CAS)
Dynamic Memory RAS & CAS Delay registers (EMCDynamicRasCas0-3 - address
0xFFE0 8104, 0xFFE0 8124, 0xFFE0 8144, 0xFFE0 8164) bit description
Static Memory Configuration registers (EMCStaticConfig0-3 - address
0xFFE0 8200, 0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit description
shows the bit assignments for the EMCStaticConfig0-3 registers. Note that
Rev. 04 — 26 August 2009
Value Description
00
01
10
11
-
0
1
-
0
1
Value Description
00
01
10
11
-
Chapter 5: LPC24XX External Memory Controller (EMC)
8 bit (POR reset value).
16 bit.
32 bit.
Reserved.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
In page mode the EMC can burst up to four external
accesses. Therefore devices with asynchronous page
mode burst four or higher devices are supported.
Asynchronous page mode burst two devices are not
supported and must be accessed normally.
Disabled (POR reset value).
Async page mode enabled (page length four).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
The value of the chip select polarity on power-on reset is
0.
Active LOW chip select.
Active HIGH chip select.
Reserved.
One CCLK cycle.
Two CCLK cycles.
Three CCLK cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
92 of 792
Reset
Value
11
NA
Reset
Value
0
NA
0
NA
0
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