LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 570
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.12 Clear Register (MCIClear - 0xE008 C038)
6.13 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C)
Table 504: Status register (MCIStatus - address 0xE008 C034) bit description
The MCIClear register is a write-only register. The corresponding static status flags can be
cleared by writing a 1 to the corresponding bit in the register.
assignment of the MCIClear register.
Table 505: Clear register (MCIClear - address 0xE008 C038) bit description
The interrupt mask registers determine which status flags generate an interrupt request by
setting the corresponding bit to 1.
MCIMaskx registers.
Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description
Bit
20
21
31:22
Bit
0
1
2
3
4
5
6
7
8
9
10
31:11
Bit
0
1
2
3
4
5
6
7
Symbol
TxDataAvlbl
RxDataAvlbl
-
Symbol
CmdCrcFailClr
DataCrcFailClr
CmdTimeOutClr
DataTimeOutClr
TxUnderrunClr
RxOverrunClr
CmdRespEndClr
CmdSentClr
DataEndClr
StartBitErrClr
DataBlockEndClr
-
Symbol
Mask0
Mask1
Mask2
Mask3
Mask4
Mask5
Mask6
Mask7
Rev. 04 — 26 August 2009
Description
Data available in transmit FIFO.
Data available in receive FIFO.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Mask CmdCrcFail flag.
Mask DataCrcFail flag.
Mask CmdTimeOut flag.
Mask DataTimeOut flag.
Mask TxUnderrun flag.
Mask RxOverrun flag.
Mask CmdRespEnd flag.
Mask CmdSent flag.
Clears RxOverrun flag.
Description
Clears CmdCrcFail flag.
Clears DataCrcFail flag.
Clears CmdTimeOut flag.
Clears DataTimeOut flag.
Clears TxUnderrun flag.
Clears CmdRespEnd flag.
Clears CmdSent flag.
Clears DataEnd flag.
Clears StartBitErr flag.
Clears DataBlockEnd flag.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table 21–506
Chapter 21: LPC24XX SD/MMC card interface
shows the bit assignment of the
Table 21–505
UM10237
© NXP B.V. 2009. All rights reserved.
shows the bit
Reset
Value
0
0
NA
Reset
Value
0
0
0
0
0
0
0
0
570 of 792
Reset
Value
-
-
-
-
-
-
-
-
-
-
-
NA
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