LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 465
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
5. Architecture
UM10237_4
User manual
Although
control, it is strongly suggested to let UART1 hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
LPC2400’s U1TER enables implementation of software and hardware flow control. When
TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon
as TXEn becomes 0, UART1 transmission will stop.
Table 17–414
Table 414. UART1 Transmit Enable Register (U1TER - address 0xE001 0030) bit description
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART1.
The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid
character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers
the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register
(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the
serial output pin, TXD1.
The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by
the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This
divided down clock is a 16x oversample clock, NBAUDOUT.
The modem interface contains registers U1MCR and U1MSR. This interface is
responsible for handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface
receives several one clock wide enables from the U1TX and U1RX blocks.
Bit
6:0
7
Symbol
-
TXEN
Table 17–414
describes how to use TXEn bit in order to achieve software flow control.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,
when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gone
true, or when it receives an XON (DC1) character.
Rev. 04 — 26 August 2009
describes how to use TxEn bit in order to achieve hardware flow
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
NA
1
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