LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 550
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024,
6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR -
Table 478: SSPn Masked Interrupt Status register (SSPnMIS -address 0xE006 801C,
0xE003 0020)
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
Table 479: SSPn interrupt Clear Register (SSP0ICR - address 0xE006 8020, SSP1ICR -
SSP1DMACR - 0xE003 0024)
The SSPnDMACR register is the DMA control register.It is a read/write register.
Table 20–480
Table 480: SSPn DMA Control Register (SSP0DMACR - address 0xE006 8024, SSP1DMACR -
Bit
0
1
2
3
7:4
Bit
0
1
7:2
Bit
0
1
15:2
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
Symbol
RORIC
RTIC
-
Symbol
Receive DMA
Enable
(RXDMAE)
Transmit DMA
Enable
(TXDMAE)
-
SSP1MIS - 0xE003 001C) bit description
0xE003 0020) bit description
0xE003 0024) bit description
shows the bit assignments of the SSPnDMACR register.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for
a "timeout period", and this interrupt is enabled.
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
Writing a 1 to this bit clears the "Rx FIFO was not empty and
has not been read for a timeout period" interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Description
When this bit is set to one 1, DMA for the receive FIFO is
enabled, otherwise receive DMA is disabled.
When this bit is set to one 1, DMA for the transmit FIFO is
enabled, otherwise transmit DMA is disabled
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 20: LPC24XX SSP interface SSP0/1
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
0
0
0
NA
Reset Value
NA
NA
NA
550 of 792
Reset
Value
0
0
NA
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