LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 58
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 58 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
3.3.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108)
3.3.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4)
3.3.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0xE01F C1A8 and
The USBCLKCFG register controls the division of the PLL output before it is used by the
USB block. If the PLL is bypassed, the division may be by 1. In that case, the PLL input
frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, the
output must be divided in order to bring the USB clock frequency to 48 MHz with a 50%
duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of
48 MHz (i.e. any mutliple of 96 MHz) within the PLL operating range.
Remark: The Internal RC clock can not be used as a clock source for USB because a
more precise clock is needed (see
Table 54.
[1]
The USB clock is derived from the PLL output signal, divided by USBSEL + 1. Having
USBSEL = 1 results in USB’s clock being one half the PLL output.
This register is used to trim the on-chip 4 MHz oscillator.
Table 55.
PCLKSEL1 - 0xE01F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal
that will be supplied to the corresponding peripheral as specified in
Table 4–57
Table 56.
Bit Symbol
3:0 USBSEL
7:4 -
Bit
7:0
15:8
Bit
1:0
3:2
5:4
7:6
9:8
Actual reset value depends on IRC factory trimming.
Symbol
PCLK_WDT
PCLK_TIMER0
PCLK_TIMER1
PCLK_UART0
PCLK_UART1
Symbol
IRCtrim
-
USB Clock Configuration register (USBCLKCFG - address 0xE01F C108) bit
description
Peripheral Clock Selection register 0 (PCLKSEL0 - address 0xE01F C1A8) bit
description
IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description
and
Table
Description
Selects the divide value for creating the USB clock from the PLL output.
Warning: Improper setting of this value will result in incorrect operation
of the USB interface.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
IRC trim value. It controls the on-chip 4 MHz IRC frequency.
Reserved. Software must write 0 into these bits.
4–58.
Rev. 04 — 26 August 2009
Description
Peripheral clock selection for WDT.
Peripheral clock selection for TIMER0.
Peripheral clock selection for TIMER1.
Peripheral clock selection for UART0.
Peripheral clock selection for UART1.
Table
Chapter 4: LPC24XX Clocking and power control
4–42).
Table
UM10237
© NXP B.V. 2009. All rights reserved.
4–56,
58 of 792
Reset
value
0xA0
NA
Reset
value
00
00
00
00
00
Reset
value
0
NA
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