LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 762
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LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 74. Dynamic Memory Percentage Command Period
Table 75. Dynamic Memory Active to Precharge Command
Table 76. Dynamic Memory Self-refresh Exit Time register
Table 77. Memory Last Data Out to Active Time register
Table 78. Dynamic Memory Data-in to Active Command
Table 79. Dynamic Memory Write recover Time register
Table 80. Dynamic Mempry Active to Active Command
Table 81. Dynamic Memory Auto-refresh Period register
Table 82. Dynamic Memory Exit Self-refresh register
Table 83. Dynamic Memory Acitve Bank A to Active Bank B
Table 84. Dynamic Memory Load Mode register to Active
Table 85. Static Memory Extended Wait register
Table 86. Dynamic Memory Configuration registers
Table 87. Address mapping . . . . . . . . . . . . . . . . . . . . . . .89
Table 88. Dynamic Memory RAS & CAS Delay registers
Table 89. Static Memory Configuration registers
Table 90. Static Memory Write Enable Delay registers
Table 91. Static Memory Output Enable delay registers
UM10237_4
User manual
0xFFE0 8028) bit description . . . . . . . . . . . . . .82
register (EMCDynamictRP - address
0xFFE0 8030) bit description . . . . . . . . . . . . . .83
Period register (EMCDynamictRAS - address
0xFFE0 8034) bit description . . . . . . . . . . . . . .83
(EMCDynamictSREX - address 0xFFE0 8038) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
(EMCDynamictAPR - address 0xFFE0 803C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Time register (EMCDynamictDAL - address
0xFFE0 8040) bit description . . . . . . . . . . . . . .85
(EMCDynamictWR - address 0xFFE0 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Period register (EMCDynamictRC - address
0xFFE0 8048) bit description . . . . . . . . . . . . . .86
(EMCDynamictRFC - address 0xFFE0 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
(EMCDynamictXSR - address 0xFFE0 8050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Time register (EMCDynamictRRD - address
0xFFE0 8054) bit description . . . . . . . . . . . . . .87
Command Time (EMCDynamictMRD - address
0xFFE0 8058) bit description . . . . . . . . . . . . . .88
(EMCStaticExtendedWait - address
0xFFE0 8080) bit description . . . . . . . . . . . . . .88
(EMCDynamicConfig0-3 - address 0xFFE0 8100,
0xFFE0 8120, 0xFFE0 8140, 0xFFE0 8160) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
(EMCDynamicRasCas0-3 - address
0xFFE0 8104, 0xFFE0 8124, 0xFFE0 8144,
0xFFE0 8164) bit description . . . . . . . . . . . . . .91
(EMCStaticConfig0-3 - address 0xFFE0 8200,
0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
(EMCStaticWaitWen0-3 - address
0xFFE0 8204,0xFFE0 8224, 0xFFE0 8244,
0xFFE0 8264) bit description . . . . . . . . . . . . . .94
(EMCStaticWaitOen03 - address 0xFFE0 8208,
0xFFE0 8228, 0xFFE0 8248, 0xFFE0 8268) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Rev. 04 — 26 August 2009
Table 92. Static Memory Read Delay registers
Table 93. Static Memory Page Mode Read Delay
Table 94. Static Memory Write Delay registers0-3
Table 95. Static Memory Trun Round Delay registers0-3
Table 96. MAM responses to program accesses of various
Table 97. MAM responses to data and DMA accesses of
Table 98. Summary of Memory Acceleration Module
Table 99. MAM Control Register (MAMCR - address
Table 100.MAM Timing register (MAMTIM - address
Table 101.Suggestions for MAM timing selection. . . . . . 108
Table 102.Summary of VIC registers . . . . . . . . . . . . . . . 110
Table 103.Software Interrupt register (VICSoftInt - address
Table 104.Software Interrupt Clear register (VICSoftIntClear
Table 105.Raw Interrupt Status register (VICRawIntr -
Table 106.Interrupt Enable register (VICIntEnable - address
Table 107.Interrupt Enable Clear register (VICIntEnClear -
Table 108.Interrupt Select register (VICIntSelect - address
Table 109.IRQ Status register (VICIRQStatus - address
Table 110. FIQ Status register (VICFIQStatus - address
Table 111. Vector Address registers 0-31 (VICVectAddr0-31 -
Table 112. Vector Priority registers 0-31 (VICVectPriority0-31
Table 113. Vector Address register (VICAddress - address
Table 114. Software Priority Mask register
Table 115. Protection Enable register (VICProtection -
Table 116. Connection of interrupt sources to the Vectored
Chapter 36: LPC24XX Supplementary information
(EMCStaticWaitRd0-3 - address 0xFFE0 820C,
0xFFE0 822C, 0xFFE0 824C, 0xFFE0 826C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
registers0-3 (EMCStaticWaitPage0-3 - address
0xFFE0 8210, 0xFFE0 8230, 0xFFE0 8250,
0xFFE0 8270) bit description . . . . . . . . . . . . . . 95
(EMCStaticWaitWr - address 0xFFE0 8214,
0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(EMCStaticWaitTurn0-3 - address 0xFFE0 8218,
0xFFE0 8238, 0xFFE0 8258, 0xFFE0 8278) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
various types . . . . . . . . . . . . . . . . . . . . . . . . . 104
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
0xE01F C000) bit description. . . . . . . . . . . . . 105
0xE01F C004) bit description. . . . . . . . . . . . . 106
0xFFFF F018) bit description. . . . . . . . . . . . . 112
- address 0xFFFF F01C) bit description . . . . 112
address 0xFFFF F008) bit description . . . . . . 113
0xFFFF F010) bit description. . . . . . . . . . . . . 113
address 0xFFFF F014) bit description . . . . . . 113
0xFFFF F00C) bit description . . . . . . . . . . . . 114
0xFFFF F000) bit description. . . . . . . . . . . . . 114
0xFFFF F004) bit description. . . . . . . . . . . . . 114
addresses 0xFFFF F100 to 0xFFFF F17C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
- addresses 0xFFFF F200 to 0xFFFF F27C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
0xFFFF FF00) bit description. . . . . . . . . . . . . 115
(VICSWPriorityMask - address 0xFFFF F024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
address 0xFFFF F020) bit description . . . . . . 116
UM10237
© NXP B.V. 2009. All rights reserved.
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