LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 692
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
10.1 Prepare sector(s) for write operation
As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC
0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers
respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The Flash memory is not accessible during a write or erase operation. IAP commands,
which results in a Flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP
Flash programming is permitted in the application.
Table 620. IAP Command Summary
This command makes Flash write/erase operation a two step process.
IAP Command
Prepare sector(s) for write operation
Copy RAM to Flash
Erase sector(s)
Blank check sector(s)
Read Part ID
Read Boot code version
Compare
Reinvoke ISP
Fig 140. IAP parameter passing
ARM REGISTER r0
ARM REGISTER r1
Rev. 04 — 26 August 2009
Chapter 30: LPC24XX Flash memory programming firmware
Command Code
50
51
52
53
54
55
56
57
10
10
10
10
10
10
10
10
COMMAND CODE
PARAMETER 1
PARAMETER 2
PARAMETER n
STATUS CODE
RESULT 1
RESULT 2
RESULT n
Described in
Table 30–621
Table 30–622
Table 30–623
Table 30–624
Table 30–625
Table 30–626
Table 30–627
Table 30–628
UM10237
command
parameter table
command
result table
© NXP B.V. 2009. All rights reserved.
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