LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 81
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh -
0xFFE0 8024)
The EMCDynamicRefresh register configures dynamic memory operation. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. However, these control bits can, if
necessary, be altered during normal operation. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
assignments for the EMCDynamicRefresh register.
Table 72.
For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wakeup period of a reset cycle. During this period, the
EMC (and all other portions of the LPC2400 that are being clocked) run from the IRC
oscillator at 4 MHz. So, 4 MHz must be considered the CCLK rate for refresh calculations
if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
Bit
10:0
31:11 -
Symbol
Refresh timer
(REFRESH)
Dynamic Memory Refresh Timer register (EMCDynamicRefresh - address
0xFFE0 8024) bit description
Rev. 04 — 26 August 2009
Value Description
0x0
0x1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Indicates the multiple of 16 CCLKs between SDRAM
refresh cycles.
Refresh disabled (POR reset value).
0x7FF = n x16 = 16n CCLKs between SDRAM refresh
cycles.
For example:
0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh
cycles.
0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh
cycles.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Table 5–72
UM10237
shows the bit
© NXP B.V. 2009. All rights reserved.
81 of 792
Reset
Value
0
NA
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