LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 580
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
7.6 Serial clock generator
7.7 Timing and control
7.8 Control register I2CONSET and I2CONCLR
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 22–119
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
This programmable clock pulse generator provides the SCL clock pulses when the I
block is in the master transmitter or master receiver mode. It is switched off when the I
block is in a slave mode. The I
via the I
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for I2DAT, enables the comparator,
generates and detects start and stop conditions, receives and transmits acknowledge bits,
controls the master and slave modes, contains interrupt request logic, and monitors the
I
The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
2
Fig 119. Serial clock synchronization
C bus status.
2
(1) Another device pulls the SCL line low before this I
(2) Another device continues to pull the SCL line low after this I
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
C control register contains bits used to control the following I
2
C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
device effectively determines the (shorter) HIGH period.
released SCL. The I
effectively determines the (longer) LOW period.
SDA line
SCL line
shows the synchronization procedure.
Rev. 04 — 26 August 2009
2
C clock generator is forced to wait until SCL goes HIGH. The other device
period
high
2
C block will stretch the SCL space duration after a byte has
2
C output clock frequency and duty cycle is programmable
(1)
period
low
Chapter 22: LPC24XX I
(2)
(3)
2
C has timed a complete high time. The other
(1)
2
C has timed a complete low time and
2
C block functions: start
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
580 of 792
2
C0/1/2
2
C
2
C
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