LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 74
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
8. Reset
9. Pin description
UM10237_4
User manual
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see the System Control
Block chapter for details of Brown-Out Detect). The other reset is from the external Reset
pin and the Watchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset. The default configuration (EMC_Reset_Disable = 0) is that both EMC
resets are asserted when any type of reset event occurs. In this mode, all registers and
functions of the EMC are initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-on
or brown-out event, in order to allow the EMC to retain its state through a warm reset
(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.
Table 5–66
Table 66.
Name
A[23:0]
D[31:0]
OE
BLS[3:0]
WE
CS[3:0]
DYCS[3:0]
CAS
RAS
Pad interface and control signal descriptions
shows the interface and control signal pins for the EMC.
Output 0x0000 0000
Output 0xF
Output 0xF
Type
Output
Output 1
Output 1
Output 0xF
Output 1
Output 1
Input/
Rev. 04 — 26 August 2009
Value on POR
reset
Data outputs =
0x0000 0000
Chapter 5: LPC24XX External Memory Controller (EMC)
Value during
self-refresh
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
Depends on
static memory
accesses
0xF
1
1
Description
External memory address output.
Used for both static and SDRAM
devices. SDRAM memories use only
bits [14:0].
External memory data lines. These
are inputs when data is read from
external memory and outputs when
data is written to external memory.
Low active output enable for static
memory devices.
Low active byte lane selects. Used
for static memory devices.
Low active write enable. Used for
SDRAM and static memories.
Static memory chip selects. Default
active LOW. Used for static memory
devices.
SDRAM chip selects. Used for
SDRAM devices.
Column address strobe. Used for
SDRAM devices.
Row address strobe. Used for
SDRAM devices.
UM10237
© NXP B.V. 2009. All rights reserved.
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