LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 718
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
5. Programming the GPDMA
UM10237_4
User manual
5.1 Enabling the GPDMA
5.2 Disabling the GPDMA
Table 651. DMA Connections
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream is
configured to provide unidirectional DMA transfers for a single source and destination.
The source and destination areas can each be either a memory region or a peripheral
which supports the GPDMA, and must be accessible through AHB1.
The following applies to the registers used in the GPDMA:
To enable the GPDMA set the DMA Enable bit in the DMACConfiguration Register
(Section 32–6.1.13 “Configuration Register (DMACConfiguration - 0xFFE0
To disable the GPDMA:
Peripheral Function DMA Single
SSP1 Rx
SD/MMC
I
I
2
2
1. Read the DMACEnbldChns Register and ensure that all the DMA channels have
2. Disable the GPDMA by writing 0 to the DMA Enable bit in the DMACConfiguration
•
•
•
•
•
S channel 0
S channel 1
Reserved or unused address locations must not be accessed because this can result
in unpredictable behavior of the device.
Reserved or unused bits of registers must be written as zero, and ignored on read
unless otherwise stated in the relevant text.
All register bits are reset to a logic 0 by a system or power-on reset unless otherwise
stated in the relevant text.
Unless otherwise stated in the relevant text, all registers support read and write
accesses. A write updates the contents of a register and a read returns the contents
of the register.
All registers defined in this document can only be accessed using word reads and
word writes (i.e. 32 bit accesses), unless otherwise stated in the relevant text.
been disabled. If any channels are active, see
channel”.
Register
- 0xFFE0 4110 and DMACC1Configuration - 0xFFE0
(Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Request Input
3
4
-
-
Rev. 04 — 26 August 2009
DMA Burst
Request Input
3
4
5
6
Section 32–5.4 “Disabling a DMA
DMA Last Word
Request Input
-
4
-
-
4130)”).
UM10237
© NXP B.V. 2009. All rights reserved.
DMA Last Burst
Request Input
-
4
-
-
4030)”.
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