LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 755
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
; /*********************************************************************
; * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts
; * generate Non Vectored IRQ request. rm_init_entry is aware
; * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts.
; * Default vector address register is programmed with the address of
; * Non vectored app_irqDispatch mentioned in this example. User can setup
; * Vectored IRQs or FIQs here.
; *********************************************************************/
; /*********************************************************************
; * Get the address of the User entry point.
; *********************************************************************/
; /*********************************************************************
; * Non vectored irq handler (app_irqDispatch)
; *********************************************************************/
AREA app_irqDispatch, CODE
VICVectAddrOffset EQU 0x30
app_irqDispatch
;User should insert code here if non vectored Interrupt sharing is
;required. Each non vectored shared irq handler must return to
;the interrupted instruction by using the following code.
;
;
;
;
;
;
;
VICBaseAddr
VICDefVectAddrOffset EQU 0x34
LDR
LDR
STR
BL
;enable FIQ and IRQ in ARM Processor
MRS
BIC
MSR
LDR
MOV
;enable interrupt nesting
STMFD sp!, {r12,r14}
MRS
MSR
MSR
MSR
STMFD sp!, {r0}
LDR
STR
LDMFD sp!, {r12,r14,r0}
SUBS pc, r14, #4
;user interrupt did not happen so call rm_irqhandler2. This handler
r0, =VICBaseAddr
r1, =app_irqDispatch
r1, [r0,#VICDefVectAddrOffset]
rm_init_entry
r1, CPSR
r1, r1, #0xC0
CPSR_c, r1
lr, =User_Entry
pc, lr
r12, spsr
cpsr_c,0x1F
cpsr_c, #0x52
spsr, r12
r0, =VICBaseAddr
r1, [r0,#VICVectAddrOffset]
Rev. 04 — 26 August 2009
EQU 0xFFFFF000 ; VIC Base address
;Initialize RealMonitor
; get the CPSR
; enable IRQs and FIQs
; update the CPSR
;Save SPSR in to r12
;Re-enable IRQ, go to system mode
;Disable irq, move to IRQ mode
;Restore SPSR from r12
;Acknowledge Non Vectored irq has finished
;Restore registers
;Return to the interrupted instruction
Chapter 35: LPC24XX RealMonitor
UM10237
© NXP B.V. 2009. All rights reserved.
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