LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 728
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and
6.2.4 Channel Control Registers (DMACC0Control - 0xFFE0 410C and
Table 668. Channel Destination Address registers (DMACC0DestAddr - address
DMACC1LLI - 0xFFE0 4128)
The two read/write DMACCxLLI Registers contain a word-aligned address of the next
Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the
DMA channel is disabled when all DMA transfers associated with it are completed.
Note: Programming this register when the DMA channel is enabled has unpredictable
side effects.
Table 32–669
Table 669. Channel Linked List Item registers (DMACC0LLI - address 0xFFE0 4108 and
Note: To make loading the LLIs more efficient for some systems, the LLI data structures
can be made four-word aligned.
DMACC0Control - 0xFFE0 412C)
The two read/write DMACCxControl Registers contain DMA channel control information
such as the transfer size, burst size, and transfer width. Each register is programmed
directly by software before the DMA channel is enabled. When the channel is enabled the
register is updated by following the linked list when a complete packet of data has been
transferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, the
channel might have progressed. It is intended to be read only when a channel has
stopped.
Bit
31:0
Bit
0
1
31:2
Symbol
DestAddr
Symbol
Reserved Reserved, read as zero, do not modify.
R
LLI
Table 32–670
0xFFE0 4104 and DMACC1DestAddr - address 0xFFE0 4124) bit description
DMACC1LLI - address 0xFFE0 4128) bit description
shows the bit assignments of the DMACCxLLI Register.
Description
Reserved, and must be written as 0, masked on read.
Linked list item. Bits [31:2] of the address for the next LLI.
Address bits [1:0] are 0.
Description
DMA destination address
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
shows the bit assignments of the DMACCxControl Register.
UM10237
© NXP B.V. 2009. All rights reserved.
NA
0
Reset Value
0
Reset Value
0x0000 0000
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