R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1087

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. Figures 21.7 and 21.8 show the operation timings in
master receive mode. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master
2. When ICDDR is read (dummy read), reception is started, the receive clock pulse is output, and
3. After the reception of the first frame data is completed, the RDRF bit in ICSR is set to 1 at the
4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time
5. If the next frame is the last receive data, set the RCVD bit in ICCRA before reading ICDRR.
6. When the RDRF bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition
7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RCVD to 0.
8. The operation returns to the slave receive mode.
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
data is received, in synchronization with the internal clock. The master mode outputs the level
specified by the ACKBT in ICIER to SDA, at the ninth receive clock pulse.
rising of the ninth receive clock pulse. At this time, the received data is read by reading
ICDRR. At the same time, RDRF is cleared.
RDRF is set. If the eighth receive clock pulse falls after reading ICDRR by other processing
while RDRF is 1, SCL is fixed to a low level until ICDRR is read.
This enables the issuance of the stop condition after the next reception.
is issued.
Master Receive Operation
Rev. 2.00 Sep. 24, 2008 Page 1053 of 1468
Section 21 I
2
C Bus Interface 2 (IIC2)
REJ09B0412-0200