R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 378

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
9.11.16 EXDMAC Cluster Transfer
Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For
details, see section 11, EXDMA Controller (EXDMAC).
Figures 9.91 and 9.92 show a read/write timing using a cluster transfer.
For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and
set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used.
Do not change the bus controller register settings during a cluster transfer.
Rev. 2.00 Sep. 24, 2008 Page 344 of 1468
REJ09B0412-0200
Figure 9.90 Output Timing Example of DACK and EDACK when DKC = 1 or EDKC = 1
DACK or EDACK
Precharge-sel
Address bus
D15 to D8
SDRAMφ
D7 to D0
and DDS = 0 or EDDS = 0 (Write)
DQMLU
DQMLL
RD/WR
RAS
CAS
CKE
WE
CS
BS
Row address
PALL
T
p
ACTV
address
Row
T
r
High
Cloumn address
NOP
T
c1
WRIT
T
c2

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