R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1119

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 22.6 shows the A/D conversion timing. Tables 22.3 and 22.4
show the A/D conversion time.
As shown in figure 22.6, the A/D conversion time (t
time (t
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 22.3 and 22.4.
In scan mode, the values given in tables 22.3 and 22.4 apply to the first conversion time. The
values given in table 22.5 apply to the second and subsequent conversions. In either case, bits
CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated
by the A/D conversion characteristics.
D
) and the input sampling time (t
Input Sampling and A/D Conversion Time
Address
Write signal
Input sampling
timing
ADF
Pφ
[Legend]
(1):
(2):
t
t
t
D:
SPL
CONV
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 22.6 A/D Conversion Timing
(1)
(2)
t
D
SPL
). The length of t
t
SPL
D
) passes after the ADST bit in ADCSR is set to
CONV
t
CONV
) includes the A/D conversion start delay
D
Rev. 2.00 Sep. 24, 2008 Page 1085 of 1468
varies depending on the timing of the
Section 22 A/D Converter
REJ09B0412-0200