R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 490

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
11.2
Table 11.1 shows the EXDMAC pin configuration.
Table 11.1 Pin Configuration
Rev. 2.00 Sep. 24, 2008 Page 456 of 1468
REJ09B0412-0200
Channel
0
1
2
3
Input/Output Pins
Name
EXDMA transfer request 0
EXDMA transfer
acknowledge 0
EXDMA transfer end 0
EDREQ0 acceptance
acknowledge
EXDMA transfer request 1
EXDMA transfer
acknowledge 1
EXDMA transfer end 1
EDREQ1 acceptance
acknowledge
EXDMA transfer request 2
EXDMA transfer
acknowledge 2
EXDMA transfer end 2
EDREQ2 acceptance
acknowledge
EXDMA transfer request 3
EXDMA transfer
acknowledge 3
EXDMA transfer end 3
EDREQ3 acceptance
acknowledge
Abbr.
EDREQ0
EDACK0
ETEND0
EDRAK0
EDREQ1
EDACK1
ETEND1
EDRAK1
EDREQ2
EDACK2
ETEND2
EDRAK2
EDREQ3
EDACK3
ETEND3
EDRAK3
I/O
Input
Output
Output
Output
Input
Output
Output
Output
Input
Output
Output
Output
Input
Output
Output
Output
Function
Channel 0 external request
Channel 0 single address transfer
acknowledge
Channel 0 transfer end
Notification to external device of
channel 0 external request
acceptance and start of execution
Channel 1 external request
Channel 1 single address transfer
acknowledge
Channel 1 transfer end
Notification to external device of
channel 1 external request
acceptance and start of execution
Channel 2 external request
Channel 2 single address transfer
acknowledge
Channel 2 transfer end
Notification to external device of
channel 2 external request
acceptance and start of execution
Channel 3 external request
Channel 3 single address transfer
acknowledge
Channel 3 transfer end
Notification to external device of
channel 3 external request
acceptance and start of execution