R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 250

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 216 of 1468
REJ09B0412-0200
Bit
15
14
13 to 12 RCW1
11
Bit Name
CMF
CMIE
RCW0

Initial
Value
0
0
0
0
0
R/W
R/(W)* Compare Match Flag
R/W
R/W
R/W
R
Description
Indicates that the refresh timer counter (RTCNT) and
refresh timer constant register (RTCOR) match.
[Clearing conditions]
•
•
[Setting condition]
•
Compare Match Interrupt Enable
Enables or disables an interrupt request (CMI) when the
CMF flag is set to 1.
This bit is effective when refresh control is not
performed (RFSHE = 0). When refresh control is
performed (RFSHE = 1), this bit is always cleared to 0.
This bit cannot be modified.
CAS-RAS Wait Control
Select the number of wait cycles inserted between the
CAS asserted cycle and CAS asserted cycle during
DRAM refresh.
When the SDRAM space is selected, these bits do not
affect operations although they can be read from or
written to.
00: No wait cycle inserted
01: One wait cycle inserted
10: Two wait cycles inserted
11: Three wait cycles inserted
Reserved
The initial value should not be changed.
When 0 is written to this bit after this bit is read as 1
with RFSHE = 0
When CBR refresh is performed with RFSHE = 1
When RTCNT matches RTCOR