R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 508

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 474 of 1468
REJ09B0412-0200
Bit
29 to 27
26
25
24
23, 22
Bit Name
RPTIE
ARS1
ARS0
Initial
value
All 0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R
Description
Reserved
They are always read as 0 and cannot be modified.
Repeat Size End Interrupt Enable
Enables or disables a repeat size end interrupt request.
When this bit is set to 1 and the next transfer source is
generated at the end of a repeat-size transfer in repeat
transfer mode, the DTE bit in EDMDR is cleared to 0. At
the same time, the ESIF bit in EDMDR is set to 1 to
indicate that a repeat size end interrupt is requested.
Even if the repeat area is not specified (ARS1, ARS0 =
B'10), the repeat size end interrupt can be requested at
the end of a repeat-size transfer.
When this bit is set to 1 and the next transfer source is
generated at the end of a block- or cluster-size transfer
in block transfer or cluster transfer mode, the DTE bit in
EDMDR is cleared to 0. At the same time, the ESIF bit
in EDMDR is set to 1 to indicate that the repeat size
end interrupt is requested.
0: Repeat size end interrupt request disabled
1: Repeat size end interrupt request enabled
Area Select 1 and 0
Select the block area or repeat area in block transfer,
repeat transfer or cluster transfer mode.
00: Block area/repeat area on the source address side
01: Block area/repeat area on the destination address
10: Block area/repeat area not specified
11: Setting prohibited
Reserved
They are always read as 0 and cannot be modified.
side

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