R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1290

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
28.2.9
The DPSRSTF bit in RSTSR indicates that deep software standby mode has been canceled by an
interrupt.
RSTSR is not initialized by the internal reset signal upon exit from deep software standby mode.
Rev. 2.00 Sep. 24, 2008 Page 1256 of 1468
REJ09B0412-0200
Bit
0
Bit
7
Bit
Bit name
Initial value:
R/W:
Notes: 1. Only 0 can be written to clear the flag.
2. Supported only by the H8SX/1668M Group.
3. Initial value is undefined in the H8SX/1668M Group.
4. Only 0 can be written to clear the flag in the H8SX/1668M Group.
5. Readable only in the H8SX/1668M Group.
Bit Name
DIRQ0EG 0
Bit Name
DPSRSTF 0
Reset Status Register (RSTSR)
DPSRSTF
R/(W)*
7
0
1
Initial
Value
Initial
Value
R/W

6
0
R/W
R/W
R/W
R/(W)* Deep Software Standby Reset Flag
R/W

5
0
Module
IRQ0 Interrupt Edge Select
Selects the active edge for IRQ0-A pin input.
0: The interrupt request is generated by a falling edge.
1: The interrupt request is generated by a rising edge.
Module
Indicates that deep software standby mode has been
canceled by an interrupt source specified in DPSIER or
DPSIEGR and an internal reset is generated.
[Setting condition]
Deep software standby mode is canceled by an interrupt
source.
[Clearing condition]
Writing a 0 to this bit after reading it as 1.
R/W

4
0
R/W

3
0
R/(W)*
LVDF*
0*
2
3
2
4
R/W
0*

1
3
PORF*
R/W*
0*
0
3
5
2