R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1479

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
28.2.7 Deep Standby
Interrupt Flag Register
(DPSIFR)
28.2.8
Interrupt Edge Register
(DPSIEGR)
28.2.9 Reset Status Register
(RSTSR)
28.2.10 Deep Standby
Backup Register (DPSBKRn)
Deep Standby
Page
1253
1254
1255
1256
1256
1258
Revision (See Manual for Details)
Amended
DPSIFR is not initialized by the internal reset signal upon
exit from deep software standby mode.
Descriptions for bits 7 to 5 R/W in the register table
R/(W)*
Descriptions for bit 3 R/W in the register table
R/(W)*
IRQ3-A input specified in DPSIEGR is generated.
Descriptions for bit 2 R/W in the register table
R/(W)*
IRQ2-A input specified in DPSIEGR is generated.
Descriptions for bit 1 R/W in the register table
R/(W)*
IRQ1-A input specified in DPSIEGR is generated.
Descriptions for bit 0 R/W in the register table
R/(W)*
IRQ0-A input specified in DPSIEGR is generated.
Amended
DPSIEGR is not initialized by the internal reset signal upon
exit from deep software standby mode.
Descriptions for bit 3 in the register table
Selects the active edge for IRQ3-A pin input.
Descriptions for bit 2 in the register table
Selects the active edge for IRQ2-A pin input.
Descriptions for bit 1 in the register table
Selects the active edge for IRQ1-A pin input.
Descriptions for bit 0 in the register table
Selects the active edge for IRQ0-A pin input.
RSTSR is not initialized by the internal reset signal upon
exit from deep software standby mode.
Amended
DPSBKRn (n=15 to 0) is not initialized by the internal reset
signal upon exit from deep software standby mode.
1
1
1
1
1
Rev. 2.00 Sep. 24, 2008 Page 1445 of 1468
Main Revisions and Additions in this Edition
REJ09B0412-0200