R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 256

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
For example, in an external address space access where the frequency rate of Iφ and Bφ is n : 1,
the operation is performed in synchronization with Bφ. In this case, external 2-state access space is
2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number
of access cycles is counted based on Iφ.
If the frequencies of Iφ, Pφ and Bφ are different, the start of bus cycle may not synchronize with
Pφ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle
(Tsy) is inserted at the beginning of each bus cycle.
For example, if an external address space access occurs when the frequency rate of Iφ and Bφ is
n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when
the frequency rate of Iφ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted.
Figure 9.6 shows the external 2-state access timing when the frequency rate of Iφ and Bφ is 4 : 1.
Figure 9.7 shows the external 3-state access timing when the frequency rate of Iφ and Bφ is 2 : 1.
Rev. 2.00 Sep. 24, 2008 Page 222 of 1468
REJ09B0412-0200

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