R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 507

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3.7
EDACR sets the operating modes and transfer methods.
Bit
31
30
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
EXDMA Address Control Register (EDACR)
Bit Name
AMS
DIRS
SARIE
DARIE
AMS
R/W
R/W
R/W
31
23
15

R
0
0
0
7
0
Initial
value
0
0
DIRS
R/W
30
22
14



R
R
R
0
0
0
6
0
R/W
R/W
R/W
SAT1
R/W
29
21
13



R
R
R
0
0
0
5
0
Description
Address Mode Select
Selects single address mode or dual address mode.
When single address mode is selected, EDACK pin is
valid due to the EDACKE bit setting in EDMDR.
0: Dual address mode
1: Single address mode
Single Address Direction Select
Specifies the data transfer direction in single address
mode. In dual address mode, the specification by this
bit is ignored.
In cluster transfer mode, the internal cluster buffer will
be the source or destination in place of the external
device with DACK.
0: EDSAR transferred as a source address
1: EDDAR transferred as a destination address
SARA4
DARA4
SAT0
R/W
R/W
R/W
28
20
12

R
0
0
0
4
0
SARA3
DARA3
R/W
R/W
27
19
11


R
R
0
0
0
3
0
Rev. 2.00 Sep. 24, 2008 Page 473 of 1468
Section 11 EXDMA Controller (EXDMAC)
DARA2
SARA2
RPTIE
R/W
R/W
R/W
26
18
10

R
0
0
0
2
0
SARA1
DARA1
ARS1
DAT1
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
REJ09B0412-0200
SARA0
DARA0
ARS0
DAT0
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0