R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 179

IC H8SX/1668 MCU FLASH 144LQFP

R5F61668RN50FPV

Manufacturer Part Number
R5F61668RN50FPV
Description
IC H8SX/1668 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61668RN50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61668RN50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. Only 0 can be written, to clear the flag.
7.3.7
SSIER selects the IRQ interrupt used to leave software standby mode.
The IRQ interrupt used to leave software standby mode should not be set as the DTC activation
source.
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
2. Supported only by the H8SX/1668M Group.
Software Standby Release IRQ Enable Register (SSIER)
Bit Name
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
SSI15
SSI7
R/W
R/W
15
7
0
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
SSI6
R/W
R/W
14
0
6
0
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
SSI5
R/W
R/W
13
0
5
0
1
1
1
1
1
1
1
1
1
1
1
1
Description
[Setting condition]
[Clearing conditions]
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQnF = 1 (n = 11 to 0)
When interrupt exception handling is executed while
low-level sensing is selected and IRQn input is high
When IRQn interrupt exception handling is executed
while falling-, rising-, or both-edge sensing is
selected
When the DTC is activated by an IRQn interrupt,
and the DISEL bit in MRB of the DTC is cleared to 0
SSI4
R/W
R/W
12
0
4
0
SSI11
SSI3
R/W
R/W
11
0
3
0
Rev. 2.00 Sep. 24, 2008 Page 145 of 1468
SSI10
SSI2
R/W
R/W
10
0
2
0
Section 7 Interrupt Controller
SSI9
SSI1
R/W
R/W
9
0
1
0
REJ09B0412-0200
SSI8
SSI0
R/W
R/W
8
0
0
0

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