R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 640

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 I/O Ports
13.1.4
ICR is an 8-bit readable/writable register that controls the port input buffers.
For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR
cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed
high.
When the pin functions as an input for the peripheral modules, the corresponding bits should be
set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input
or is used as an analog input/output pin.
When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value
is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral
module.
If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR
should be modified when the corresponding input pins are not used. For example, an IRQ input,
modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the
interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the
ICR setting, the edge should be cancelled.
The initial value of ICR is H'00.
Rev. 2.00 Sep. 24, 2008 Page 606 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial Value
R/W
Notes: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower five bits are valid and the upper three bits are reserved for port M registers.
Bits 2 and 3 are valid and the other bits are reserved for port C registers.
Registers of ports J and K cannot be accessed when PCJKE = 0.
Registers of ports D and E cannot be accessed when PCJKE = 1.
Input Buffer Control Register (PnICR) (n = 1, 2, 3, 5, 6, A to F, H to K, and M)
Pn7ICR
R/W
7
0
Pn6ICR
R/W
6
0
Pn5ICR
R/W
5
0
Pn4ICR
R/W
4
0
Pn3ICR
R/W
3
0
Pn2ICR
R/W
2
0
Pn1ICR
R/W
1
0
Pn0ICR
R/W
0
0