ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 150

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

17.5
8151H–AVR–02/11
Output Compare Unit
Figure 17-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the
output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global inter-
rupt flag in SREG is set), the output compare flag generates an output compare interrupt. The
OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform genera-
tor uses the match signal to generate an output according to operating mode set by the
WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used
by the waveform generator for handling the special cases of the extreme values in some modes
count
direction
clear
clk
top
bottom
Tn
DATA BUS
T2
TCNTn
is present or not. A CPU write overrides (has priority over) all counter clear or
T2
). clk
direction
Increment or decrement TCNT2 by 1.
Select between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT2 has reached maximum value.
Signalize that TCNT2 has reached minimum value (zero).
153.
T2
count
clear
bottom
can be generated from an external or internal clock source,
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
( From Prescaler )
Clock Select
Detector
Edge
T0
ATmega128A
in the following.
Tn
150