ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 267

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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8151H–AVR–02/11
Table 24-5.
Signal
Name
HOLD
IREFEN
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
Boundary-scan Signals for the ADC (Continued)
Direction
as Seen
from the
ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Sample & Hold signal.
Sample analog signal
when low. Hold signal
when high. If gain stages
are used, this signal
must go active when
ACLK is high.
Enables Band-gap
reference as AREF
signal to DAC
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative
input for differential
signal, bit 2
Input Mux for negative
input for differential
signal, bit 1
Input Mux for negative
input for differential
signal, bit 0
Enable pass-gate of gain
stages.
Precharge output latch of
comparator. (Active low)
Switch-cap TEST
enable. Output from x10
gain stage send out to
Port Pin having ADC_4
Output of gain stages will
settle faster if this signal
is high first two ACLK
periods after AMPEN
goes high.
Selects Vcc as the ACC
reference voltage.
Recommen-
ded Input
when not
in Use
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
ATmega128A
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
267

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