ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 38
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ATMEGA128A-AU
Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128A-AU
Manufacturer:
ATMEL
Quantity:
9 000
Company:
Part Number:
ATMEGA128A-AU
Manufacturer:
ATMEL
Quantity:
3 480
Part Number:
ATMEGA128A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8.1.3
8.1.4
8.1.5
8.1.6
8151H–AVR–02/11
Flash Clock – clk
Asynchronous Timer Clock – clk
ADC Clock – clk
XDIV - XTAL Divide Control Register
The Flash clock controls operatio
n of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Coun-
ter as a real-time counter even when the device is in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The XTAL Divide Control Register is used to divide the Source clock frequency by a number in
the range 2 - 129. This feature can be used to decrease power consumption when the require-
ment for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk
clk
can be written run-time to vary the clock frequency as suitable to the application.
• Bits 6:0 – XDIV6:XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of
these bits is denoted d, the following formula defines the resulting CPU and peripherals clock
frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to
one, the value written simultaneously into XDIV6:XDIV0 is taken as the division factor. When
XDIVEN is written to zero, the value written simultaneously into XDIV6:XDIV0 is rejected. As the
divider divides the master clock input to the MCU, the speed of all peripherals is reduced when a
division factor is used.
When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only.
The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the
scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0
registers may fail.
Bit
Read/Write
Initial Value
ADC
FLASH
ADC
, clk
CPU
CLK
, clk
:
XDIVEN
R/W
FLASH
7
0
ASY
) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit
XDIV6
R/W
6
0
XDIV5
R/W
5
0
f
CLK
=
XDIV4
R/W
4
0
Source clock
--------------------------------- -
129 d
XDIV3
–
R/W
3
0
XDIV2
R/W
2
0
XDIV1
ATmega128A
R/W
1
0
XDIV0
R/W
0
0
XDIV
I/O
38
,