ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 25

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

7.5.6
7.5.7
8151H–AVR–02/11
Pull-up and Bus-keeper
Timing
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
Atmel
Table
before selecting the wait-state. The most important parameters are the access time for the exter-
nal memory compared to the set-up requirement of the ATmega128A. The access time for the
External Memory is defined to be the time from receiving the chip select/address until the data of
this address actually is driven on the bus. The access time cannot exceed the time from the ALE
pulse must be asserted low until data is stable during a read sequence (See t
in Tables 27-9 through Tables 27-16 on pages 332 - 335). The different wait-states are set up in
software. As an additional feature, it is possible to divide the external memory space in two sec-
tors with individual wait-state settings. This makes it possible to connect two different memory
devices with different timing requirements to the same XMEM interface. For XMEM interface tim-
ing details, please refer to
“External Data Memory Timing” on page
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 7-6.
System Clock (CLK
®
7-4. It is important to consider the timing specification of the External Memory device
AVR
35. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
®
ATmega128A XMEM interface provides four different wait-states as shown in
External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
DA7:0
A15:8
CPU
ALE
WR
RD
)
Prev. addr.
Prev. data
Prev. data
Prev. data
Table 27-9
T1
to
332.
Table 27-16
Address
Address
Address
“XMCRB - External Memory Control Register B”
T2
XX
XXXXX
and
Address
Figure 27-9
T3
Data
Data
Data
ATmega128A
to
XXXXXXXX
T4
Figure 27-12
LLRL
+ t
RLRH
- t
in the
DVRH
25