ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 24

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

7.5.5
8151H–AVR–02/11
Address Latch Requirements
The control bits for the External Memory Interface are located in three registers, the MCU Con-
trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External
Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 7-6
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the External Memory Interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
octal latch (typically “74 × 573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8MHz @ 4V and 4MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
9 through Tables 27-16 on pages 332 - 335. The D-to-Q propagation delay (t
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
Figure 7-5.
• RD: Read strobe.
• WR: Write strobe.
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
(this figure shows the wave forms without wait-states). When ALE goes from high-to-low,
External SRAM Connected to the Atmel
h
Figure 7-5
= 5 ns. Refer to t
AVR
illustrates how to connect an external SRAM to the AVR using an
AD7:0
A15:8
ALE
WR
PD
RD
SU
).
) must not exceed address valid to ALE low (t
LAXX_LD
SU
).
TH
/t
LLAXX_ST
).
D
G
Q
in
“External Data Memory Timing”
®
AVR
®
“I/O Ports” on page
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
ATmega128A
PD
AVLLC
) must be taken
65. The XMEM
) minus PCB
Tables 27-
Fig-
24