ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 155

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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8151H–AVR–02/11
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2 and TCNT2.
Figure 17-6. Fast PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-
ting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM21:0 to 3 (see
will only be visible on the port pin if the data direction for the port pin is set as output. The PWM
waveform is generated by setting (or clearing) the OC2 Register at the compare match between
OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the coun-
ter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a
constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform
generated will have a maximum frequency of f
ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output
compare unit is enabled in the fast PWM mode.
TCNTn
OCn
OCn
Period
1
2
3
f
OCnPWM
4
OC2
Table 17-4 on page
=
= f
----------------- -
N 256
f
clk_I/O
5
clk_I/O
/2 when OCR2 is set to zero. This fea-
6
160). The actual OC2 value
7
ATmega128A
OCRn Interrupt Flag Set
OCRn Update
and
TOVn Interrupt Flag Set
(COMn1:0 = 2)
(COMn1:0 = 3)
155

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