ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 273

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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8151H–AVR–02/11
Table 24-7.
Bit Number
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
ATmega128A Boundary-scan Order (Continued)
Signal Name
RSTT
RSTHV
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TWIEN
PD0.Data
PD0.Control
PD0.Pullup_Enable
PD1.Data
PD1.Control
PD1.Pullup_Enable
PD2.Data
PD2.Control
PD2.Pullup_Enable
PD3.Data
PD3.Control
PD3.Pullup_Enable
PD4.Data
PD4.Control
PD4.Pullup_Enable
PD5.Data
PD5.Control
PD5.Pullup_Enable
PD6.Data
PD6.Control
PD6.Pullup_Enable
PD7.Data
PD7.Control
PD7.Pullup_Enable
PG0.Data
Module
Reset Logic
(Observe-only)
Enable signals for main Clock/Oscillators
Clock input and Oscillators for the main clock
(Observe-only)
TWI
Port D
Port G
ATmega128A
273

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