ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 51

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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10. System Control and Reset
10.1
10.2
8151H–AVR–02/11
Resetting the AVR
Reset Sources
During Reset, all I/O registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute
jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the interrupt vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the interrupt
vectors are in the Boot section or vice versa. The circuit diagram in
logic. The the electrical parameters of the reset circuitry are defined in
acteristics” on page
The I/O ports of the Atmel
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the CKSEL fuses. The different selec-
tions for the delay period are presented in
The ATmega128A has five sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
• Brown-out Reset. The MCU is reset when the supply voltage V
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one
threshold (V
than the minimum pulse length.
Watchdog is enabled.
Reset threshold (V
of the scan chains of the JTAG system. Refer to the section
scan” on page 255
POT
).
324.
BOT
for details.
) and the Brown-out Detector is enabled.
®
AVR
®
are immediately reset to their initial state when a reset source
“Clock Sources” on page
“IEEE 1149.1 (JTAG) Boundary-
CC
Figure 10-1
39.
is below the Brown-out
ATmega128A
“System and Reset Char-
shows the reset
51

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