ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 210

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

8151H–AVR–02/11
Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
After all TWI Register updates and other pending application software tasks have been com-
pleted, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to
TWINT clears the flag. The TWI will then commence executing whatever operation was speci-
fied by the TWCR setting.
4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and
5. The application software should now examine the value of TWSR, to make sure that the
6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and
7. The application software should now examine the value of TWSR, to make sure that the
• When the TWI has finished an operation and expects application response, the TWINT flag is
• When the TWINT flag is set, the user must update all TWI Registers with the value relevant
set. The SCL line is pulled low until TWINT is cleared.
for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be
transmitted in the next bus cycle.
cation software might take some special action, like calling an error routine. Assuming
that the status code is as expected, the application must load SLA+W into TWDR.
Remember that TWDR is used both for address and data. After TWDR has been
loaded with the desired SLA+W, a specific value must be written to TWCR, instructing
the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is
described later on. However, it is important that the TWINT bit is set in the value written.
Writing a one to TWINT clears the flag. The TWI will not start any operation as long as
the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT,
the TWI will initiate transmission of the address packet.
TWSR is updated with a status code indicating that the address packet has success-
fully been sent. The status code will also reflect whether a slave acknowledged the
packet or not.
address packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must load a data packet into TWDR. Subsequently, a specific value
must be written to TWCR, instructing the TWI hardware to transmit the data packet
present in TWDR. Which value to write is described later on. However, it is important
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immedi-
ately after the application has cleared TWINT, the TWI will initiate transmission of the
data packet.
TWSR is updated with a status code indicating that the data packet has successfully
been sent. The status code will also reflect whether a slave acknowledged the packet or
not.
data packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some spe-
cial action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to TWCR, instructing the TWI hardware to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the TWINT bit is set in the value written. Writing a one to TWINT clears
the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission
of the STOP condition. Note that TWINT is NOT set after a STOP condition has been
sent.
ATmega128A
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