ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 383

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

8151H–AVR–02/11
23 Analog to Digital Converter ................................................................ 233
24 JTAG Interface and On-chip Debug System ..................................... 250
25 Boot Loader Support – Read-While-Write Self-Programming ......... 277
22.3
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
23.9
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
24.10
24.11
24.12
24.13
24.14
24.15
24.16
25.1
25.2
25.3
25.4
25.5
25.6
Register Description ......................................................................................231
Features ........................................................................................................233
Overview ........................................................................................................233
Operation .......................................................................................................234
Starting a Conversion ....................................................................................235
Prescaling and Conversion Timing ................................................................236
Changing Channel or Reference Selection ...................................................238
ADC Noise Canceler .....................................................................................239
ADC Conversion Result .................................................................................243
Register Description ......................................................................................245
Features ........................................................................................................250
Overview ........................................................................................................250
TAP – Test Access Port ................................................................................251
TAP Controller ...............................................................................................252
Using the Boundary-scan Chain ....................................................................253
Using the On-chip Debug System .................................................................253
On-chip Debug Specific JTAG Instructions ...................................................254
Using the JTAG Programming Capabilities ...................................................255
Bibliography ...................................................................................................255
IEEE 1149.1 (JTAG) Boundary-scan .............................................................255
Data Registers ...............................................................................................256
Boundary-scan Specific JTAG Instructions ...................................................258
Boundary-scan Chain ....................................................................................259
ATmega128A Boundary-scan Order .............................................................269
Boundary-scan Description Language Files ..................................................276
Register Description ......................................................................................276
Features ........................................................................................................277
Overview ........................................................................................................277
Application and Boot Loader Flash Sections .................................................277
Read-While-Write and No Read-While-Write Flash Sections ........................278
Boot Loader Lock Bits ...................................................................................280
Entering the Boot Loader Program ................................................................281
ATmega128A
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