ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 80
ATMEGA128A-AU
Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435
Available stocks
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8151H–AVR–02/11
Table 12-12. Overriding Signals for Alternate Functions PD7:PD4
Table 12-13. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins
PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT3/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT3 ENABLE
1
INT3 INPUT
–
PD7/T2
0
0
0
0
0
0
0
0
T2 INPUT
–
PD2/INT2/RXD1
RXEN1
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
1
INT2 INPUT/RXD1
–
PD6/T1
0
0
0
0
0
0
0
0
T1 INPUT
–
PD5/XCK1
0
0
0
0
UMSEL1
XCK1 OUTPUT
0
0
XCK1 INPUT
–
PD1/INT1/SDA
TWEN
PORTD1 • PUD
TWEN
SDA_OUT
TWEN
0
INT1 ENABLE
1
INT1 INPUT
SDA INPUT
(1)
ATmega128A
PD0/INT0/SCL
TWEN
PORTD0 • PUD
TWEN
SCL_OUT
TWEN
0
INT0 ENABLE
1
INT0 INPUT
SCL INPUT
PD4/ICP1
0
0
0
0
0
0
0
0
ICP1 INPUT
–
80
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