ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 1050

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.5.17
Name:
Addresses: 0x400B004C [0], 0x400B0074 [1], 0x400B009C [2], 0x400B00C4 [3]
Access:
Reset:
• SRC_DSCR
0: Source address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the source.
• DST_DSCR
0: Destination address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the destination.
• FC
This field defines which device controls the size of the buffer transfer, also referred as to the Flow Controller.
• SRC_INCR
1050
31
23
15
–
–
–
7
–
SRC_INCR
SAM3U Series
DMAC Channel x [x = 0..3] Control B Register
000
001
010
011
FC
00
10
DMAC_CTRLBx [x = 0..3]
Read-write
0x00000000
IEN
30
22
14
–
6
–
FC
Peripheral-to-Peripheral
Type of addressing mode
Memory-to-Peripheral
Peripheral-to-Memory
Memory-to-Memory
INCREMENTING
Type of transfer
29
21
13
–
5
–
FIXED
DST_INCR
DST_DSCR
28
20
12
–
4
–
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Flow Controller
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
25
17
–
9
–
1
–
SRC_INCR
6430D–ATARM–25-Mar-11
SRC_DSCR
24
16
8
–
0
–