ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 804

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

37.5
37.5.1
37.5.2
37.5.3
37.6
Figure 37-3. High Speed MultiMedia Memory Card Bus Topology
804
Product Dependencies
Bus Topology
SAM3U Series
I/O Lines
Power Management
Interrupt
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with
PIO lines. The programmer must first program the PIO controllers to assign the peripheral func-
tions to HSMCI pins.
Table 37-2.
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer
must first configure the PMC to enable the HSMCI clock.
The HSMCI interface has an interrupt line connected to the Nested Vector Interrupt Controller
(NVIC).
Handling the HSMCI interrupt requires programming the NVIC before configuring the HSMCI.
Table 37-3.
Instance
Instance
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
HSMCI
I/O Lines
Peripheral IDs
17
ID
1
9 1011
2 3 4 5 6
MMC
1213 8
MCCDA
MCDA0
MCDA1
MCDA2
MCDA3
MCDA4
MCDA5
MCDA6
MCDA7
Signal
MCCK
7
I/O Line
PC28
PC29
PC30
PC31
PA4
PA3
PA5
PA6
PA7
PA8
6430D–ATARM–25-Mar-11
Peripheral
B
B
B
B
A
A
A
A
A
A