ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 892
![IC MCU 32BIT 256KB FLSH 100TFBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATSAM3U4CA-CU
Manufacturer Part Number
ATSAM3U4CA-CU
Description
IC MCU 32BIT 256KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3U4CA-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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38.6.5.6
38.6.5.7
892
892
SAM3U Series
SAM3U Series
Interrupts
Write Protect Registers
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can
be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 regis-
ter), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx
in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or
according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a
read operation in the PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt
remains active until a read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and
PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the
PWM_IDR1 and PWM_IDR2 registers.
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the field WPCMD in the
on page 926
There are two types of Write Protect:
Both types of Write Protect can be applied independently to a particular register group by means
of the WPCMD and WPRG fields in PWM_WPCR register. If at least one Write Protect is active,
• Register group 0:
• Register group 1:
• Register group 2:
• Register group 3:
• Register group 4:
• Register group 5:
• Write Protect SW, which can be enabled or disabled.
• Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller
can disable it.
–
–
–
–
–
–
–
–
–
–
“PWM Clock Register” on page 897
“PWM Disable Register” on page 899
“PWM Sync Channels Mode Register” on page 905
“PWM Channel Mode Register” on page 933
“PWM Channel Period Register” on page 937
“PWM Channel Period Update Register” on page 938
“PWM Channel Dead Time Register” on page 940
“PWM Channel Dead Time Update Register” on page 941
“PWM Fault Mode Register” on page 920
“PWM Fault Protection Value Register” on page 923
(PWM_WPCR). They are divided into 6 groups:
“PWM Write Protect Control Register”
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
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