ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 147
ATSAM3U4CA-CU
Manufacturer Part Number
ATSAM3U4CA-CU
Description
IC MCU 32BIT 256KB FLSH 100TFBGA
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U4CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
57
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
52K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b, 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
52 KB
Interface Type
3xUSART, TWI, 4xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
57
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3U4CA-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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13.16.1.4
13.16.1.5
6430D–ATARM–25-Mar-11
B
BLE
B.W
BEQ
BEQ.W
BL
BX
BXNE
BLX
Condition flags
Examples
loopA
ng
target ; Branch to target within 16MB range
target ; Conditionally branch to target
target ; Conditionally branch to target within 1MB
funC
LR
R0
R0
; Branch to loopA
; Conditionally branch to label ng
; Branch with link (Call) to function funC, return address
; stored in LR
; Return from function call
; Conditionally branch to address stored in R0
; Branch with link and exchange (Call) to a address stored
; in R0
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it
has a longer branch range when it is inside an IT block.
These instructions do not change the flags.
• do not use PC in the BLX instruction
• for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target
• when any of these instructions is inside an IT block, it must be the last instruction of the IT
address created by changing bit[0] to 0
block.
SAM3U Series
147
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