ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 620

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.11
Name:
Address:
Access:
• SPIWPVS: SPI Write Protection Violation Status
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
620
620
31
23
15
–
–
7
–
SPIWPVS value
SAM3U Series
SAM3U Series
SPI Write Protection Status Register
0x1
0x2
0x3
0x4
0x5
0x6
0x7
30
22
14
SPI_WPSR
0x400080E8
Read-only
–
–
6
–
The Write Protection has blocked a Write access to a protected register (since the last read).
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx).
Both Write Protection violation and software reset with Write Protection enabled have occurred
since the last read.
Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
The Write Protection has blocked a Write access to a protected register and write accesses have
been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select
“i” was active) since the last read.
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx) and some write
accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while
the Chip Select “i” was active) since the last read.
- The Write Protection has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protection was enabled.
and
- Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
29
21
13
–
–
5
–
28
20
12
–
–
4
–
SPIWPVSRC
27
19
11
–
–
3
–
Violation Type
26
18
10
–
–
2
SPIWPVS
25
17
–
–
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
24
16
–
–
8
0