ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 195

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.20.10 System Handler Control and State Register
• USGFAULTENA
Usage fault enable bit, set to 1 to enable
• BUSFAULTENA
Bus fault enable bit, set to 1 to enable
• MEMFAULTENA
Memory management fault enable bit, set to 1 to enable
• SVCALLPENDED
SVC call pending bit, reads as 1 if exception is pending
• BUSFAULTPENDED
Bus fault exception pending bit, reads as 1 if exception is pending
• MEMFAULTPENDED
Memory management fault exception pending bit, reads as 1 if exception is pending
• USGFAULTPENDED
Usage fault exception pending bit, reads as 1 if exception is pending
• SYSTICKACT
SysTick exception active bit, reads as 1 if exception is active
• PENDSVACT
PendSV exception active bit, reads as 1 if exception is active
1.
2.
3.
6430D–ATARM–25-Mar-11
SVCALLPENDE
SVCALLAVCT
31
23
15
D
7
Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of
status of the exceptions.
the exceptions, but see the Caution in this section.
BUSFAULTPEND
ED
30
22
14
6
The SHCSR enables the system handlers, and indicates:
See the register summary in
ments are:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
MEMFAULTPEN
Reserved
Reserved
DED
29
21
13
5
(3)
(1)
USGFAULTPEND
28
20
12
ED
4
Table 13-30 on page 180
(2)
(3)
Reserved
(3)
USGFAULTACT
SYSTICKACT
(2)
27
19
11
3
(2)
USGFAULTENA
PENDSVACT
Reserved
for the SHCSR attributes. The bit assign-
26
18
10
2
(2)
BUSFAULTENA
BUSFAULTACT
SAM3U Series
Reserved
25
17
9
1
MEMFAULTENA
MEMFAULTACT
MONITORACT
24
16
8
0
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