ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 668

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 34-3. Start Bit Detection
Figure 34-4. Character Reception
34.4.2.3
Figure 34-5. Receiver Ready
34.4.2.4
668
RXRDY
URXD
SAM3U Series
Sampling Clock
S
Receiver Ready
Receiver Overrun
Baud Rate
D0
Example: 8-bit, parity enabled 1 stop
Sampling
URXD
Clock
URXD
D1
D2
When a complete character is received, it is transferred to the UART_RHR and the RXRDY sta-
tus bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register UART_RHR is read.
If UART_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with
the bit RSTSTA (Reset Status) at 1.
period
0.5 bit
D3
True Start Detection
period
1 bit
D4
D0
D5
D6
D1
True Start
Detection
D7
D2
P
D3
S
D4
Read UART_RHR
D0
D5
D1
D6
D2
D3
D7
Parity Bit
D4
D5
Stop Bit
D6
6430D–ATARM–25-Mar-11
D7
D0
P