ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 688

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

35.6
35.6.1
688
688
Product Dependencies
SAM3U Series
SAM3U Series
I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The program-
mer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up
on TXD must also be enabled.
All the pins of the modems may or may not be implemented on the USART. On USARTs not
equipped with the corresponding pin, the associated control bits and statuses have no effect on
the behavior of the USART.
Table 35-3.
Instance
USART0
USART0
USART0
USART0
USART0
USART0
USART0
USART0
USART0
USART1
USART1
USART1
USART1
USART1
USART2
USART2
USART2
USART2
USART2
USART3
USART3
USART3
USART3
USART3
I/O Lines
Signal
DCD0
DSR0
DTR0
RXD0
SCK0
RXD1
SCK1
RXD2
SCK2
RXD3
SCK3
CTS0
RTS0
TXD0
CTS1
RTS1
TXD1
CTS2
RTS2
TXD2
CTS3
RTS3
TXD3
RI0
I/O Line
PC10
PC11
PC13
PC19
PC12
PB11
PB10
PB12
PB22
PB21
PA19
PA17
PA18
PA23
PA22
PA21
PA24
PA20
PA23
PA25
PA22
PB8
PB9
PB7
Peripheral
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
A
B
B
B
B
A
A
A
A
B
B
A
B
A
B
B
A
B
A
B
B
B
A
B