ATSAM3U4CA-CU Atmel, ATSAM3U4CA-CU Datasheet - Page 129

• Manufacturer Part Number: ATSAM3U4CA-CU
• Description: IC MCU 32BIT 256KB FLSH 100TFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b, 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 52 KB
• Interface Type: 3xUSART, TWI, 4xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 57
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.12.5
13.12.5.1
13.12.5.2
13.12.5.3
13.12.5.4
13.12.5.5
6430D–ATARM–25-Mar-11
CMP
CMN
CMPGT
CMP and CMN
Syntax
Operation
Restrictions
Condition flags
Examples
R2, R9
R0, #6400
SP, R7, LSL #2
Compare and Compare Negative.
where:
cond
Rn
Operand2
details of the options.
These instructions compare the value in a register with Operand2. They update the condition
flags on the result, but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as
a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an
ADDS instruction, except that the result is discarded.
In these instructions:
These instructions update the N, Z, C and V flags according to the result.
• do not use PC
• Operand2 must not be SP.
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
is an optional condition code, see
is the register holding the first operand.
is a flexible second operand. See
“Conditional execution” on page
“Flexible second operand” on page 96
SAM3U Series
100.
129
for